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* future product?ontact factory for availability. 19-3052; rev 1; 2/04 general description the MAX1304?ax1306/max1308?ax1310/max1312 max1314 12-bit, analog-to-digital converters (adcs) offer eight, four, or two independent input channels. independent track- and-hold (t/h) circuitry provides simultaneous sampling for each channel. the MAX1304/ max1305/max1306 provide a 0 to +5v input range with ?v fault-tolerant inputs. the max1308/max1309/ max1310 provide a ?v input range with ?6.5v fault-tol- erant inputs. the max1312/max1313/max1314 have a ?0v input range with ?6.5v fault-tolerant inputs. these adcs convert two channels in 0.9?, and up to eight channels in 1.98?, with an 8-channel throughput of 456ksps per channel. other features include a 20mhz t/h input bandwidth, internal clock, internal (+2.5v) or external (+2.0v to +3.0v) reference, and power-saving modes. a 20mhz, 12-bit, bidirectional parallel data bus pro- vides the conversion results and accepts digital inputs that activate each channel individually. all devices operate from a +4.75v to +5.25v analog supply and a +2.7v to +5.25v digital supply and consume 57ma total supply current when fully operational. each device is available in a 48-pin 7mm x 7mm tqfp package and operates over the extended -40? to +85? temperature range. applications sin/cos position encoder multiphase motor control multiphase power monitoring power-grid synchronization power-factor monitoring vibration and waveform analysis features ? up to eight channels of simultaneous sampling 8ns aperture delay 100ps channel-to-channel t/h match ? extended input ranges 0 to +5v (MAX1304/max1305/max1306) -5v to +5v (max1308/max1309/max1310) -10v to +10v (max1312/max1313/max1314) ? fast conversion time one channel in 0.72s two channels in 0.9s four channels in 1.26s eight channels in 1.98s ? high throughput 1075ksps/channel for one channel 901ksps/channel for two channels 680ksps/channel for four channels 456ksps/channel for eight channels ? 1 lsb inl, 0.9 lsb dnl (max) ? 84dbc sfdr, -86dbc thd, 71db sinad, f in = 500khz at 0.4dbfs ? 12-bit, 20mhz, parallel interface ? internal or external clock ? +2.5v internal reference or +2.0v to +3.0v external reference ? +5v analog supply, +3v to +5v digital supply 55ma analog supply current 1.3ma digital supply current shutdown and power-saving modes ? 48-pin tqfp package (7mm x 7mm footprint) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ________________________________________________________________ maxim integrated products 1 for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information pin configurations appear at end of data sheet. part temp range pin-package MAX1304 ecm -40 c to +85 c 48 tqfp max1305 ecm -40 c to +85 c 48 tqfp max1306 ecm* -40 c to +85 c 48 tqfp max1308 ecm -40 c to +85 c 48 tqfp max1309 ecm -40 c to +85 c 48 tqfp max1310 ecm* -40 c to +85 c 48 tqfp max1312 ecm -40 c to +85 c 48 tqfp max1313 ecm -40 c to +85 c 48 tqfp max1314 ecm* -40 c to +85 c 48 tqfp selector guide part input range (v) channel count MAX1304ecm 0 to +5 8 max1305ecm 0 to +5 4 max1306ecm 0 to +5 2 max1308ecm ? 8 max1309ecm ? 4 max1310ecm ? 2 max1312ecm ?0 8 max1313ecm ?0 4 max1314ecm ?0 2
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipo- lar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see figures 3 and 4.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ch0?h7, i.c. to agnd (MAX1304/max1305/max1306)....?v ch0?h7, i.c. to agnd (max1308/max1309/max1310)..?6.5v ch0?h7, i.c. to agnd (max1312/max1313/max1314)..?6.5v d0?11 to dgnd ....................................-0.3v to (dv dd + 0.3v) eoc , eolc , rd , wr , cs to dgnd .........-0.3v to (dv dd + 0.3v) convst, clk, shdn, chshdn to dgnd ..-0.3v to (dv dd + 0.3v) intclk/ extclk to agnd .......................-0.3v to (av dd + 0.3v) ref ms , ref, msv to agnd.....................-0.3v to (av dd + 0.3v) ref+, com, ref- to agnd.....................-0.3v to (av dd + 0.3v) maximum current into any pin except av dd , dv dd , agnd, dgnd ...........................................................................?0ma continuous power dissipation (t a = +70?) tqfp (derate 22.7mw/? above +70?) ................1818.2mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static performance (note 1) resolution n 12 bits integral nonlinearity inl (note 2) ?.5 ?.0 lsb differential nonlinearity dnl no missing codes (note 2) ?.3 ?.9 lsb unipolar, 0x000 to 0x001 ? ?6 offset error bipolar, 0xfff to 0x000 ? ?6 lsb unipolar, between all channels 9 ?0 offset-error matching bipolar, between all channels 9 ?0 lsb unipolar, 0x000 to 0x001 7 offset-error temperature drift bipolar, 0xfff to 0x000 7 ppm/? gain error ? ?6 lsb gain-error matching between all channels ? ?4 lsb gain-error temperature drift 4 ppm/? dynamic performance at f in = 500khz, a in = -0.4dbfs (note 2) signal-to-noise ratio snr 68 71 db signal-to-noise plus distortion sinad 68 71 db total harmonic distortion thd -86 -80 dbc spurious-free dynamic range sfdr 84 dbc channel-to-channel isolation 80 86 db analog inputs (ch0 through ch7) MAX1304/max1305/max1306 0 +5 max1308/max1309/max1310 -5 +5 input voltage v ch max1312/max1313/max1314 -10 +10 v
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipo- lar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see figures 3 and 4.) parameter symbol conditions min typ max units MAX1304/max1305/max1306 7.58 max1308/max1309max1310 8.66 input resistance (note 3) r ch max1312/max1313/max1314 14.26 k ? track/hold one channel selected for conversion 1075 two channels selected for conversion 901 four channels selected for conversion 680 external-clock throughput rate (note 4) f th eight channels selected for conversion 456 ksps one channel selected for conversion 983 two channels selected for conversion 821 four channels selected for conversion 618 internal-clock throughput rate (note 4, table 1) f th eight channels selected for conversion 413 ksps small-signal bandwidth 20 mhz full-power bandwidth 20 mhz aperture delay t ad 8ns aperture-delay matching 100 ps aperture jitter t aj 50 ps rms internal reference ref output voltage v ref 2.475 2.500 2.525 v reference output-voltage temperature drift 30 ppm/? ref ms output voltage v refms 2.475 2.500 2.525 v ref+ output voltage v ref+ 3.850 v com output voltage v com 2.600 v ref- output voltage v ref- 1.350 v differential reference voltage v ref+ - v ref - 2.500 v
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units external reference (ref and ref ms are externally driven) ref input voltage range v ref 2.0 2.5 3.0 v ref input resistance r ref (note 5) 5 k ? ref input capacitance 15 pf ref ms input voltage range v refms 2.0 2.5 3.0 v ref ms input resistance r refms (note 6) 5 k ? ref ms input capacitance 15 pf ref+ output voltage v ref+ v ref = +2.5v 3.850 v com output voltage v com v ref = +2.5v 2.600 v ref- output voltage v ref- v ref = +2.5v 1.350 v differential reference voltage v ref+ - v ref - v ref = +2.5v 2.500 v digital inputs (d0?7, rd , wr , cs , clk, shdn, chshdn , convst) input-voltage high v ih 0.7 x dv dd v input-voltage low v il 0.3 x dv dd v input hysteresis 20 mv input capacitance c in 15 pf input current i in v in = 0 or dv dd 0.02 ? ? clock-select input (intclk/ extclk ) input-voltage high v ih 0.7 x av dd v input-voltage low v il 0.3 x av dd v digital outputs (d0?11, eoc , eolc ) output-voltage high v oh i source = 0.8ma, figure 1 dv dd - 0.6 v output-voltage low v ol i sink = 1.6ma, figure 1 0.4 v d0?11 tri-state leakage current rd = high or cs = high 0.06 1a d 0d 11 tr i - s tate outp ut c ap aci tance rd = high or cs = high 15 pf power supplies analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.70 5.25 v MAX1304/max1305/max1306, all channels selected 55 60 max1308/max1309/max1310, all channels selected 54 60 analog supply current i avdd max1312/max1313/max1314, all channels selected 54 60 ma electrical characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipo- lar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see figures 3 and 4.)
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units MAX1304/max1305/max1306, all channels selected 1.3 2.6 max1308/max1309/max1310, all channels selected 1.3 2.6 digital supply current (c load = 100pf) (note 7) i dvdd max1312/max1313/max1314, all channels selected 1.3 2.6 ma i avdd shdn = dv dd , v ch = float 0.6 10 shutdown current (note 8) i dvdd shdn = dv dd , rd = wr = high 0.02 1 ? power-supply rejection ratio psrr av dd = +4.75v to +5.25v 50 db timing characteristics (figure 1) internal clock, figure 7 800 900 ns time to first conversion result t conv external clock, figure 8 12 clk cycles internal clock, figure 7 200 225 ns time to subsequent conversions t next external clock, figure 8 3 clk cycles convst pulse-width low (acquisition time) t acq (note 9) figures 6?0 0.1 1000.0 ? cs pulse width t cs figure 6 30 ns rd pulse-width low t rdl figures 7, 8, 9 30 ns rd pulse-width high t rdh figures 7, 8, 9 30 ns wr pulse-width low t wrl figure 6 30 ns cs to wr t ctw figure 6 (note 10) ns wr to cs t wtc figure 6 (note 10) ns cs to rd t ctr figures 7, 8, 9 (note 10) ns rd to cs t rtc figures 7, 8, 9 (note 10) ns data access time ( rd low to valid data) t acc figures 7, 8, 9 30 ns bus relinquish time ( rd high) t req figures 7, 8, 9 5 30 ns clk rise to eoc delay t eocd figure 8 20 ns clk rise to eolc fall delay t eolcd figure 8 20 ns convst fall to eolc rise delay t cveolcd figures 7, 8, 9 20 ns internal clock, figure 7 50 ns eoc pulse width t eoc external clock, figure 8 1 clk cycle electrical characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipo- lar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see figures 3 and 4.)
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 6 _______________________________________________________________________________________ note 1: for the MAX1304/max1305/max1306, v in = 0 to +5v. for the max1308/max1309/max1310, v in = -5v to +5v. for the max1312/max1313/max1314, v in = -10v to +10v. note 2: all channel performance is guaranteed by correlation to a single channel test. note 3: the analog input resistance is terminated to an internal bias point (figure 5). calculate the analog input current using: for v ch within the input voltage range. note 4: throughput rate is given per channel. throughput rate is a function of clock frequency (f clk ). the external clock through- put rate is specified with f clk = 16.67mhz and the internal clock throughput rate is specified with f clk = 15mhz. see the data throughput section for more information. note 5: the ref input resistance is terminated to an internal +2.5v bias point (figure 2). calculate the ref input current using: for v ref within the input voltage range. note 6: the ref ms input resistance is terminated to an internal +2.5v bias point (figure 2). calculate the ref ms input current using: for v refms within the input voltage range. note 7: all analog inputs are driven with a -0.4dbfs 500khz sine wave. note 8: shutdown current is measured with the analog input floating. the large amplitude of the maximum shutdown current speci- fication is due to automated test equipment limitations. note 9: convst must remain low for at least the acquisition period. the maximum acquisition time is limited by internal capacitor droop . note 10: cs to wr and cs to rd are internally and together. setup and hold times do not apply. note 11: minimum clk frequency is limited only by the internal t/h droop rate. limit the time between the rising edge of convst and the falling edge of eolc to a maximum of 1ms. i vv r refms refms refms = ? 25 . i vv r ref ref ref = ? 25 . i vv r ch ch bias ch _ _ _ = ? parameter symbol conditions min typ max units input-data setup time t dtw figure 6 10 ns input-data hold time t wtd figure 6 10 ns external clk period t clk figures 8, 9 0.05 10.00 ? external clk high period t clkh logic sensitive to rising edges, figures 8, 9 20 ns external clk low period t clkl logic sensitive to rising edges, figures 8, 9 20 ns external clock frequency f clk (note 11) 0.1 20 mhz internal clock frequency f int 15 mhz convst high to clk edge t cntc figures 8, 9 20 ns electrical characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipo- lar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), shdn = dgnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see figures 3 and 4.)
t ypical operating characteristics (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipolar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), f in = 500khz, a in = -0.4dbfs. t a = +25?, unless otherwise noted.) (figures 3 and 4) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 7 integral nonlinearity vs. digital output code MAX1304 toc01 digital output code inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0409 6 differential nonlinearity vs. digital output code MAX1304 toc02 digital output code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 04 096 MAX1304 toc03 av dd (v) offset error (lsb) 5.2 5.1 5.0 4.9 4.8 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 4.7 5.3 offset error vs. analog supply voltage offset error vs. temperature MAX1304 toc04 temperature ( c) offset error (lsb) 60 35 -15 10 -12 -8 -4 0 4 8 12 16 -16 -40 85 MAX1304 toc05 av dd (v) gain error (lsb) 5.2 5.1 5.0 4.9 4.8 -4 -3 -2 -1 0 1 -5 4.7 5.3 gain error vs. analog supply voltage gain error vs. temperature MAX1304 toc06 temperature ( c) gain error (lsb) 60 35 -15 10 -12 -8 -4 0 4 8 12 16 -16 -40 85
t ypical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipolar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), f in = 500khz, a in = -0.4dbfs. t a = +25?, unless otherwise noted.) (figures 3 and 4) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 8 _______________________________________________________________________________________ output histogram (dc input) MAX1304 toc10 digital output code counts 2048 2047 2046 2045 1000 2000 3000 4000 5000 6000 0 2044 00 1084 5497 1611 small-signal bandwidth vs. analog input frequency MAX1304 toc07 analog input frequency (mhz) gain (db) 10 1 -10 -8 -6 -4 -2 0 2 -12 0.1 100 a in = -20dbfs large-signal bandwidth vs. analog input frequency MAX1304 toc08 analog input frequency (mhz) gain (db) 10 1 -10 -8 -6 -4 -2 0 2 -12 0.1 100 a in = -0.5dbfs fft plot (2048-point data record) MAX1304 toc09 frequency (khz) amplitude (dbfs) 300 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 100 200 400 500 f th = 1.04167msps f in = 500khz a in = -0.05dbfs snr = 70.7db sinad = 70.6db thd = -87.5dbc sfdr = 87.1dbc
t ypical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipolar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), f in = 500khz, a in = -0.4dbfs. t a = +25?, unless otherwise noted.) (figures 3 and 4) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges _______________________________________________________________________________________ 9 -100 -95 -90 -85 -80 -75 -70 -65 -60 0510 15 20 25 total harmonic distortion vs. clock frequency MAX1304 toc13 f clk (mhz) thd (dbc) 60 65 70 75 80 85 90 95 100 0510 15 20 25 spurious-free dynamic range vs. clock frequency MAX1304 toc14 f clk (mhz) sfdr (dbc) 60 66 64 62 68 70 72 74 76 78 80 010 5152 025 signal-to-noise ratio vs. clock frequency MAX1304 toc11 f clk (mhz) snr (db) 60 66 64 62 68 70 72 74 76 78 80 010 5152025 signal-to-noise plus distortion vs. clock frequency MAX1304 toc12 f clk (mhz) sinad (db)
t ypical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipolar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), f in = 500khz, a in = -0.4dbfs. t a = +25?, unless otherwise noted.) (figures 3 and 4) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 10 ______________________________________________________________________________________ signal-to-noise ratio vs. reference voltage MAX1304 toc15 v ref (v) snr (db) 2.8 2.6 2.4 2.2 66 67 68 69 70 71 72 73 74 75 65 2.0 3.0 signal-to-noise plus distortion vs. reference voltage MAX1304 toc16 v ref (v) sinad (db) 2.8 2.6 2.4 2.2 66 67 68 69 70 71 72 73 74 75 65 2.0 3.0 total harmonic distortion vs. reference voltage MAX1304 toc17 v ref (v) thd (dbc) 2.8 2.6 2.4 2.2 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -90 2.0 3.0 spurious-free dynamic range vs. reference voltage MAX1304 toc18 v ref (v) sfdr (dbc) 2.8 2.6 2.4 2.2 75 80 85 90 95 100 70 2.0 3.0
t ypical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipolar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), f in = 500khz, a in = -0.4dbfs. t a = +25?, unless otherwise noted.) (figures 3 and 4) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 11 digital supply current vs. digital supply voltage MAX1304 toc20 dv dd (v) i dvdd (ma) 5.0 4.5 4.0 3.5 3.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.6 2.5 5.5 t a = +85 c t a = +25 c t a = -40 c c load = 50pf MAX1304 toc21 av dd (v) i avdd (na) 5.2 5.1 5.0 4.9 4.8 520 540 560 580 600 620 640 660 680 700 500 4.7 5.3 analog shutdown current vs. analog supply voltage digital shutdown current vs. digital supply voltage MAX1304 toc22 dv dd (v) i dvdd (na) 5.0 4.5 4.0 3.5 3.0 12 14 16 18 20 22 10 2.5 5.5 analog supply current vs. number of channels selected MAX1304 toc23 number of channels selected i avdd (ma) 8 7 6 5 4 3 2 1 40 35 45 50 55 60 30 0 chshdn = 0 analog supply current vs. analog supply voltage MAX1304 toc19 av dd (v) i avdd (ma) 5.2 5.1 5.0 4.9 4.8 52 53 54 55 56 57 51 4.7 5.3 t a = +85 c t a = +25 c t a = -40 c digital supply current vs. number of channels selected MAX1304 toc24 number of channels selected i dvdd (ma) 8 7 6 5 4 3 2 1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.9 1.0 0.1 0 chshdn = 0
t ypical operating characteristics (continued) (av dd = +5v, dv dd = +3v, agnd = dgnd = 0, v ref = v refms = +2.5v (external reference), c ref = c refms = 0.1?, c ref+ = c ref- = 0.1?, c ref+-to-ref- = 2.2? || 0.1?, c com = 2.2? || 0.1?, c msv = 2.2? || 0.1? (unipolar devices), msv = agnd (bipolar devices), f clk = 16.67mhz 50% duty cycle, intclk/ extclk = agnd (external clock), f in = 500khz, a in = -0.4dbfs. t a = +25?, unless otherwise noted.) (figures 3 and 4) MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 12 ______________________________________________________________________________________ internal reference voltage vs. analog supply voltage MAX1304 toc25 av dd (v) v ref (v) 5.2 5.1 4.8 4.9 5.0 2.4997 2.4998 2.4999 2.5000 2.5001 2.5002 2.5003 2.5004 2.4996 4.7 5.3 internal reference voltage vs. temperature MAX1304 toc26 temperature ( c) v ref (v) 60 35 -15 10 2.497 2.498 2.499 2.500 2.501 2.502 2.503 2.504 2.496 -40 85 internal clock conversion time vs. analog supply voltage MAX1304 toc27 av dd (v) time (ns) 5.2 5.1 5.0 4.9 4.8 100 200 300 400 500 600 700 800 900 0 4.7 5.3 t next t conv internal clock conversion time vs. temperature MAX1304 toc28 temperature ( c) time (ns) 60 35 10 -15 180 200 780 800 820 160 -40 85 t next t conv MAX1304 toc29 v ch_ (v) i ch_ (ma) 4 2 0 -2 -4 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 2.0 -2.0 -6 6 analog input channel current vs. analog input channel voltage MAX1304/max1305/max1306 -3.0 -2.5 -1.0 -0.5 -1.5 -2.0 0 0.5 1.0 2.0 2.5 1.5 3.0 -20 -15 -10 -5 0 5 10 15 20 analog input channel current vs. analog input channel voltage MAX1304 toc30 v ch_ (v) i ch_ (ma) max1308/max1309/max1310 -2.0 -1.0 -1.5 0 -0.5 0.5 1.0 1.5 2.0 -20 -10 -5 -15 0 5 1 01520 analog input channel current vs. analog input channel voltage MAX1304 toc31 v ch_ (v) i ch_ (ma) max1312/max1313/max1314
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 13 pin description pin MAX1304 max1308 max1312 max1305 max1309 max1313 max1306 max1310 max1314 name function 1, 15, 17 1, 15, 17 1, 15, 17 av dd analog power input. av dd is the power input for the analog section of the converter. apply +5v to av dd . connect all av dd pins together. see the layout, grounding, and bypassing section for additional information. 2, 3, 14, 16, 23 2, 3, 14, 16, 23 2, 3, 14, 16, 23 agnd analog ground. agnd is the power return for av dd . connect all agnd pins together. 44 4 ch0 channel 0 analog input 55 5 ch1 channel 1 analog input 666msv midscale voltage bypass. for the unipolar MAX1304/max1305/max1306, connect a 2.2? and a 0.1? capacitor from msv to agnd. for the bipolar max1308/max1309/max1310/max1312/max1313/max1314, connect msv to agnd. 77 ch2 channel 2 analog input 88 ch3 channel 3 analog input 9 ch4 channel 4 analog input 10 ch5 channel 5 analog input 11 ch6 channel 6 analog input 12 ch7 channel 7 analog input 13 13 13 intclk/ extclk clock-mode select input. connect intclk/ extclk to av dd to select the internal clock. connect intclk/ extclk to agnd to use an external clock connected to clk. 18 18 18 ref ms midscale reference bypass or input. ref ms connects through a 5k ? resistor to the internal +2.5v bandgap reference buffer. for the MAX1304/max1305/max1306 unipolar devices, v refms is the input to the unity-gain buffer that drives msv. msv sets the midpoint of the input voltage range. for internal reference operation, bypass ref ms with a 0.01? capacitor to agnd. for external reference operation, drive ref ms with an external voltage from +2v to +3v. for the max1308/max1309/max1310/max1312/max1313/max1314 bipolar devices, connect ref ms to ref. for internal reference operation, bypass the ref ms /ref node with a 0.01? capacitor to agnd. for external reference operation, drive the ref ms /ref node with an external voltage from +2v to +3v. 19 19 19 ref adc reference bypass or input. ref connects through a 5k ? resistor to the internal +2.5v bandgap reference buffer. for internal reference operation, bypass ref with a 0.01? capacitor. for external reference operation with the MAX1304/max1305/max1306 unipolar devices, drive ref with an external voltage from +2v to +3v. for external reference operation with the max1308/max1309/max1310/ max1312/max1313/max1314 bipolar devices, connect ref ms to ref and drive the ref ms /ref node with an external voltage from +2v to +3v.
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 14 ______________________________________________________________________________________ pin description (continued) pin MAX1304 max1308 max1312 max1305 max1309 max1313 max1306 max1310 max1314 name function 20 20 20 ref+ positive reference bypass. bypass ref+ with a 0.1? capacitor to agnd. also bypass ref+ to ref- with a 2.2? and a 0.1? capacitor. v ref+ = v com + v ref / 2. 21 21 21 com reference common bypass. bypass com to agnd with a 2.2? and a 0.1? capacitor. v com = 13 / 25 x av dd . 22 22 22 ref- negative reference bypass. bypass ref- with a 0.1? capacitor to agnd. also bypass ref- to ref+ with a 2.2? and a 0.1? capacitor. v ref+ = v com - v ref / 2. 24, 39 24, 39 24, 39 dgnd digital ground. dgnd is the power return for dv dd . connect all dgnd pins together. 25, 38 25, 38 25, 38 dv dd digital power input. dv dd powers the digital section of the converter, including the parallel interface. apply +2.7v to +5.25v to dv dd . bypass dv dd to dgnd with a 0.1? capacitor. connect all dv dd pins together. 26 26 26 d0 d i g i tal i/o 0 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 27 27 27 d1 d i g i tal i/o 1 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 28 28 28 d2 d i g i tal i/o 2 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 29 29 29 d3 d i g i tal i/o 3 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 30 30 30 d4 d i g i tal i/o 4 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 31 31 31 d5 d i g i tal i/o 5 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 32 32 32 d6 d i g i tal i/o 6 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 33 33 33 d7 d i g i tal i/o 7 of 12- bi t p ar al l el d ata bus. h i g h i m p ed ance w hen rd = 1 or cs = 1. 34 34 34 d8 digital output 8 of 12-bit parallel data bus. high impedance when rd = 1 or cs = 1. 35 35 35 d9 digital output 9 of 12-bit parallel data bus. high impedance when rd = 1 or cs = 1. 36 36 36 d10 digital output 10 of 12-bit parallel data bus. high impedance when rd = 1 or cs = 1. 37 37 37 d11 digital output 11 of 12-bit parallel data bus. high impedance when rd = 1 or cs = 1. 40 40 40 eoc e nd - of- c onver si on output. eoc goes low to i nd i cate the end of a conver si on. it r etur ns hi g h on the next r i si ng c lk ed g e or the fal l i ng c on v s t ed g e. 41 41 41 eolc end-of-last-conversion output. eolc goes low to indicate the end of the last conversion. it returns high when convst goes low for the next conversion sequence. 42 42 42 rd read inp u t. p ul l i ng rd l ow i ni ti ates a r ead com m and of the p ar al l el d ata b us. 43 43 43 wr write input. pulling wr low initiates a write command for configuring the device with d0?7.
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 15 detailed description the MAX1304?ax1306/max1308?ax1310/max1312 max1314 are 12-bit adcs. the devices offer 8, 4, or 2 independently selectable input channels, each with dedicated t/h circuitry. simultaneous sampling of all active channels preserves relative phase information making these devices ideal for motor control and power monitoring. three input ranges are available, 0 to +5v, ?v and ?0v. the 0 to +5v devices provide ?v fault- tolerant inputs. the ?v and ?0v devices provide ?6.5v fault-tolerant inputs. two-channel conversion results are available in 0.9?. conversion results from all eight channels are available in 1.98?. the 8-chan- nel throughput is 456ksps per channel. internal or external reference and clock capability offer great flexi- bility, and ease of use. a write-only configuration regis- ter can mask out unused channels and a shutdown feature reduces power. a 20mhz, 12-bit, parallel data bus outputs the conversion results. figure 2 shows the functional diagram of these adcs. 100pf device pin v dd i ol = 1.6ma i oh = 0.8ma 1.6v figure 1. digital load test circuit pin description (continued) pin MAX1304 max1308 max1312 max1305 max1309 max1313 max1306 max1310 max1314 name function 44 44 44 cs chip-select input. pulling cs low activates the digital interface. forcing cs high places d0?11 in high-impedance mode. 45 45 45 c on v s t conversion start input. driving convst high initiates the conversion process. the analog inputs are sampled on the rising edge of convst. 46 46 46 clk external clock input. for external clock operation, connect intclk/ extclk to dgnd and drive clk with an external clock signal from 100khz to 20mhz. for internal clock operation, connect intclk/ extclk to dv dd and connect clk to dgnd. 47 47 47 shdn shutdown input. driving shdn high initiates device shutdown. connect shdn to dgnd for normal operation. 48 48 48 chshdn active-low analog-input channel-shutdown input. drive chshdn low to power down analog inputs that are not selected for conversion in the configuration register. drive chshdn high to power up all analog input channels regardless of whether they are selected for conversion in the configuration register. see the channel shutdown ( chshdn ) section for more information. 9, 10, 11, 12 7, 8, 9, 10, 11, 12 i.c. internally connected. connect i.c. to agnd.
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 16 ______________________________________________________________________________________ MAX1304?ax1306 max1308?ax1310 max1312?ax1314 convst d11 msv dgnd av dd shdn intclk/extclk clk ch0 interface and control 8 x 1 mux 12-bit adc ch7 d0 dv dd agnd chshdn ref ms ref ref+ com ref- t/h t/h 8 x 12 sram output drivers 5k ? 5k ? configuration register d7 d8 2.500v * *switch closed on unipolar devices, open on bipolar devices wr cs rd eoc eolc figure 2. functional diagram
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 17 max1308 max1312 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 d0 d1 d2 d3 d4 d5 d7 d8 d9 d10 d11 av dd agnd dv dd dgnd msv ref ms ref ref+ com ref- +5v gnd +2.7v to +5.25v gnd cs wr bipolar analog inputs para llel digital output convst rd digital interface and control 4 5 7 8 9 10 11 12 2, 3, 14, 16, 23 21 22 20 19 18 6 17 48 47 46 25, 38 45 44 43 42 41 40 37 36 35 34 33 d6 32 31 30 29 28 27 26 24, 39 av dd av dd 15 1 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f 2.2 f 2.2 f bipolar configuration chshdn shdn clk eolc eoc intclk/extclk 13 figure 3. typical bipolar operating circuit
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 18 ______________________________________________________________________________________ MAX1304 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 d0 d1 d2 d3 d4 d5 d7 d8 d9 d10 d11 av dd agnd dv dd dgnd msv ref ms ref ref+ com ref- +5v gnd +2.7v to +5.25v gnd cs wr unipolar analog inputs p arallel digital output convst rd digital interface and control 4 5 7 8 9 10 11 12 2, 3, 14, 16, 23 21 22 20 19 18 6 17 48 47 46 25, 38 45 44 43 42 41 40 37 36 35 34 33 d6 32 31 30 29 28 27 26 24, 39 av dd av dd 15 1 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f 2.2 f 2.2 f unipolar configuration 0.1 f 2.2 f chshdn shdn clk eolc eoc intclk/extclk 13 0.01 f figure 4. typical unipolar operating circuit
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 19 analog inputs track and hold (t/h) to preserve phase information across the multichannel MAX1304?ax1306/max1308?ax1310/max1312 max1314, all input channels have dedicated t/h ampli- fiers. figure 5 shows the equivalent analog input t/h circuit for one channel. the input t/h circuit is controlled by the convst input. when convst is low, the t/h circuit tracks the analog input. when convst is high the t/h circuit holds the analog input. the rising edge of convst is the analog input sampling instant. there is an aperture delay (t ad ) of 8ns and a 50ps rms aperture jitter (t aj ). the aperture delay of each dedicated t/h input is matched within 100ps of each other. to settle the charge on c sample to 12-bit accuracy, use a minimum acquisition time (t acq ) of 100ns. therefore, convst must be low for at least 100ns. although longer acquisition times allow the analog input to settle to its final value more accurately, the maximum acquisition time must be limited to 1ms. accuracy with conversion times longer than 1ms cannot be guaran- teed due to capacitor droop in the input circuitry. due to the analog input resistive divider formed by r1 and r2 in figure 5, any significant analog input source resistance (r source ) results in gain error. further- more, r source causes distortion due to nonlinear analog input currents. limit r source to a maximum of 100 ? . selecting an input buffer to improve the input signal bandwidth under ac condi- tions, drive the input with a wideband buffer (>50mhz) that can drive the adc? input capacitance (15pf) and settle quickly. for example, the max4431 or the max4265 can be used for the 0 to +5v unipolar devices, or the max4350 can be used for ?v bipolar inputs. most applications require an input buffer to achieve 12-bit accuracy. although slew rate and bandwidth are impor- tant, the most critical input buffer specification is settling time. the simultaneous sampling of multiple channels requires an acquisition time of 100ns. at the beginning of the acquisition, the adc internal sampling capacitor array connects to the analog inputs, causing some distur- bance. ensure the amplifier is capable of settling to at least 12-bit accuracy during this interval. use a low-noise, low-distortion, wideband amplifier that settles quickly and is stable with the adc? 15pf input capacitance. see the maxim website at www.maxim-ic.com for appli- cation notes on how to choose the optimum buffer amplifier for your adc application. input bandwidth the input-tracking circuitry has a 20mhz small-signal bandwidth, making it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. input range and protection the MAX1304/max1305/max1306 provide a 0 to +5v input voltage range with fault protection of ?v. the max1308/max1309/max1310 provide a ?v input volt- age range with fault protection of ?6.5v. the max1312/max1313/max1314 provide a ?0v input voltage range with fault protection of ?6.5v. figure 5 shows the single-channel equivalent input circuit. ch_ undervoltage protection clamp overvoltage protection clamp r1 2.5pf av dd c sample c hold MAX1304?ax1306 max1308?ax1310 max1312?ax1314 r1 | | r2 = 2k ? r2 v bias *r source analog signal source *minimize r source to avoid gain error and distortion. input range (v) part 0 to +5 MAX1304 max1305 max1306 max1308 max1309 max1310 max1312 max1313 max1314 5 10 r1 (k ? ) 3.33 6.67 13.33 r2 (k ? ) v bias (v) 5.00 2.86 2.35 0.90 2.50 2.06 figure 5. single-channel, equivalent analog input t/h circuit
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 20 ______________________________________________________________________________________ data throughput the data throughput (f th ) of the MAX1304?ax1306/ max1308?ax1310/max1312?ax1314 is a function of the clock speed (f clk ). in internal clock mode, f clk = 15mhz (typ). in external clock mode, 100khz f clk 20mhz. when reading during conversion (figures 7 and 8), calculate f th as follows: where n is the number of active channels and t quiet is the period of bus inactivity before the rising edge of convst. see the starting a conversion section for more information. table 1 uses the above equation and shows the total throughput as a function of the number of channels selected for conversion. clock modes the MAX1304?ax1306/max1308?ax1310/max1312 max1314 provide a 15mhz internal conversion clock. alternatively, an external clock can be used. internal clock internal clock mode frees the microprocessor from the burden of running the adc conversion clock. for inter- nal clock operation, connect intclk/ extclk to av dd and connect clk to dgnd. note that intclk/ extclk is referenced to av dd , not dv dd . external clock for external clock operation, connect intclk/ extclk to agnd and connect an external clock source to clk. note that intclk/ extclk is referenced to av dd , not dv dd . the external clock frequency can be up to 20mhz. linearity is not guaranteed with clock frequen- cies below 100khz due to droop in the t/h circuits. f tt xn f th acq quiet clk = ++ + ? + 1 12 3 1 1 () table 1. throughput vs. channels sampled: f clk = 15mhz, t acq = 100ns, t quiet = 50ns channels sampled (n) clock cycles until last result clock cycle for reading last conversion total conversion time (ns) total throughput ( ksps) throughput per channel (f th ) 112 1 800 983 983 21 51 1000 1643 821 31 81 1200 2117 705 42 11 1400 2474 618 52 41 1600 2752 550 62 71 1800 2975 495 73 01 2000 3157 451 83 31 2200 3310 413
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 21 applications information digital interface the bidirectional parallel digital interface allows for setting the 8-bit configuration register (see the configuration register section) and reading the 12-bit conversion result. the interface includes the following control signals: chip select ( cs ), read ( rd ), write ( wr ), end of conversion ( eoc ), end of last conversion ( eolc ), conversion start (convst), shutdown (shdn), channel shutdown ( chshdn ), internal clock select (intclk/ extclk ), and external clock input (clk). figures 6, 7, 8, 9, table 2, and the timing characteristics show the operation of the inter- face. d0?7 are bidirectional, and d8?11 are output only. d0?11 go high impedance when rd = 1 or cs = 1. configuration register enable channels as active by writing to the configura- tion register through i/o lines d0?7 (table 2). the bits in the configuration register map directly to the chan- nels, with d0 controlling channel zero, and d7 control- ling channel seven. setting any bit high activates the corresponding input channel, while resetting any bit low deactivates the corresponding channel. on the devices with less than eight channels, some of the bits have no function (table 2). to write to the configuration register, pull cs and wr low, load bits d0 through d7 onto the parallel bus, and force wr high. the data are latched on the rising edge of wr (figure 6). write to the configuration register at any point during the conversion sequence. however, the new configuration does not take effect until the next convst falling edge. at power-up all channels default active. shutdown does not change the configuration register. the configuration register may be written to in shutdown. see the channel shutdown ( chshdn ) section for information about using the con- figuration register for power saving. table 2. configuration register bit/channel part number state d0/ch0 d1/ch1 d2/ch2 d3/ch3 d4/ch4 d5/ch5 d6/ch6 d7/ch7 on* 1 1 1 1 1111 MAX1304 max1308 max1312 off 0 0 0 0 0000 on* 1 111xxxx max1305 max1309 max1313 off 0 000xxxx on* 1 1 x x xxxx max1306 max1310 max1314 off 0 0 x x xxxx * power-up state. x = don? care, (must be 1 or 0). d0?7 data-in rd convst configuration register updates cs wr t cs t wrl t ctw t dtw t wtd t wtc figure 6. write timing
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 22 ______________________________________________________________________________________ starting a conversion to start a conversion using internal clock mode, pull convst low for the acquisition time (t acq ). the t/h acquires the signal while convst is low, and conver- sion begins on the rising edge of convst. the end-of- conversion signal ( eoc ) pulses low whenever a conversion result becomes available for read. the end- of-last-conversion signal ( eolc ) goes low when the last conversion result is available (figure 7). to start a conversion using external clock mode, pull convst low for the acquisition time (t acq ). the t/h acquires the signal while convst is low. the rising edge of convst is the sampling instant. apply an external clock to clk to start the conversion. to avoid t/h droop degrading the sampled analog input signals, the first clk pulse must occur within 10? from the rising edge of convst. additionally, the external clock frequency must be greater than 100khz to avoid t/h droop-degrading accuracy. the first conversion result is available for read when eoc goes low on the rising edge of the 13th clock cycle. subsequent conversion results are available after every third clock cycle there- after (figures 8 and 9). in both internal and external clock modes, hold convst high until the last conversion result is read. if convst goes low in the middle of a conversion, the current conversion is aborted and a new conversion is initiated. furthermore, there must be a period of bus inactivity (t quiet ) for 50ns or longer before the falling edge of convst for the specified adc performance. convst ch0 track hold d0?11 sample instant t acq t eoc t acc t ctr t rdh t rtc t rdl t req track ch1 t conv t next eoc t cveolcd t quiet 50ns eolc cs* rd *cs can be low at all times, low during the rd cycles, or the same as rd. figure 7. read during conversion?hannel 0 and channel 1 selected, internal clock
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 23 reading a conversion result reading during a conversion figures 7 and 8 show the interface signals to initiate a read operation during a conversion cycle. these figures show two channels selected for conversion. if more channels are selected, the results are available succes- sively at every eoc falling edge. cs can be low at all times, low during the rd cycles, or the same as rd . after initiating a conversion by bringing convst high, wait for eoc to go low. in internal clock mode, eoc goes low within 900ns. in external clock mode, eoc goes low on the rising edge of the 13th clk cycle. to read the conversion result, drive cs and rd low to latch data to the parallel digital output bus. bring rd high to release the digital bus. in internal clock mode, the next eoc falling edge occurs within 225ns. in exter- nal clock mode, the next eoc falling edge occurs in three clk cycles. when the last result is available eolc goes low. reading after conversion figure 9 shows the interface signals for a read operation after a conversion with all eight channels enabled. at the falling of eolc , driving cs and rd low places the first conversion result onto the parallel bus. successive low pulses of rd place the successive conversion results onto the bus. when the last conversion results in the sequence are read, additional read pulses wrap the pointer back to the first converted result. convst clk ch3 track hold d0?11 sample instant t acq t cntc t ctr t rdh t rtc t acc t rdl t req track ch7 eoc rd 12312 13 14 15 16 17 18 19 1 t clk t eocd t conv t next t eoc t eocd t clkh t eolcd t cveolcd t quiet 50ns t clkl eolc cs* *cs can be low at all times, low during the rd cycles, or the same as rd. figure 8. read during conversion?hannel 3 and channel 7 selected, external clock
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 24 ______________________________________________________________________________________ power-up reset at power-up, all channels are selected for conversion (see the configuration register section). after applying power, allow the 1ms wake-up time to elapse and then initiate a dummy conversion and discard the results. after the dummy conversion is complete, accurate con- versions can be obtained. power-saving modes shutdown mode during shutdown the internal reference and analog circuits in the device shutdown and the analog supply current drops to 0.6? (typ). select shutdown mode using the shdn input. set shdn high to enter shut- down mode. shdn takes precedence over chshdn . entering and exiting shutdown mode does not change the configuration byte. however, a new configuration byte can be written while in shutdown mode by follow- ing the standard write procedure shown in figure 6. eoc and eolc are high when the MAX1304?ax1306/ max1308?ax1310/max1312?ax1314 are shut down. the state of the digital outputs d0?11 is independent of the state of shdn. if cs and rd are low, the digital outputs d0?11 are active regardless of shdn. the digital outputs only go high impedance when cs or rd is high. when the digital outputs are powered down, the digital supply current drops to 20na. exiting shutdown (falling edge of shdn) starts a con- version in the same way as the rising edge of convst. after coming out of shutdown, initiate a dummy conver- sion and discard the results. after the dummy conver- sion, allow the 1ms wake-up time to expire before initiating the first accurate conversion. channel shutdown ( c c h h s s h h d d n n ) the channel-shutdown feature allows analog input channels to be powered down when they are not selected for conversion. powering down channels that are not selected for conversion reduces the analog supply current by 2.9ma per channel. to power down channels that are not selected for conversion, pull chshdn low. see the configuration register section for information on selecting and deselecting channels for conversion. the drawback of powering down analog inputs that are not selected for conversion is that it takes time to power them up. figure 10 shows how a dummy conversion is used to power up an analog input in external clock mode. after selecting a new channel in the configura- tion register, initiate a dummy conversion and discard the results. after the dummy conversion, allow the 1ms wake-up time (t wake ) to expire before initiating the first accurate conversion. d0?11 convst t ctr t acc t req t rdl t rdh t rtc t cveolcd t eoc t quiet1 = 50ns ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 only last pulse shown eoc rd cs* eolc * cs can be low at all times, low during the rd cycles, or the same as rd. figure 9. read after conversion?ight channels selected, external clock
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 25 convst clk eoc cs* eolc t acq t acq dummy conversion start configuration register powers up one or more channels first accurate conversion start configuration register updates 12345 1213 1 t w ake 1ms wr d0?7 *cs can be low at all times, low during the rd cycles, or the same as rd. d ata in figure 10. powering up an analog input channel with a dummy conversion and wake-up time ( chshdn = 0, external-clock mode, one channel selected) convst clk eoc cs* eolc t acq t acq first accurate conversion start configuration register powers up one or more channels second accurate conversion start configuration register updates 12345 1213 1 wr d0?7 *cs can be low at all times, low during the rd cycles, or the same as rd. d ata in figure 11. powering up an analog input channel directly ( chshdn = 1, external-clock mode, one channel selected)
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 26 ______________________________________________________________________________________ to avoid the timing requirements associated with pow- ering up an analog channel, force chshdn high. with chshdn high, each analog input is powered up regardless of whether it is selected for conversion in the configuration register. note that shutdown mode takes precedence over the chshdn mode. reference internal reference the internal reference circuits provide for analog input voltages of 0 to +5v for the unipolar MAX1304/ max1305/max1306, 5v for the bipolar max1308/ max1309/max1310 or 10v for the bipolar max1312/ max1313/max1314. install external capacitors for ref- erence stability, as indicated in table 3 and shown in figures 3 and 4. as illustrated in figure 2, the internal reference voltage is 2.5v (v ref ). this 2.5v is internally buffered to create the voltages at ref+ and ref-. table 4 shows the volt- ages at com, ref+, and ref-. external reference external reference operation is achieved by overriding the internal reference voltage. override the internal ref- erence voltage by driving ref with a +2.0v to +3.0v external reference. as shown in figure 2, the ref input impedance is 5k ? . for more information about using external references see the transfer functions section. midscale voltage (msv) the voltage at msv (v msv ) sets the midpoint of the adc transfer functions. for the 0 to +5v input range (unipolar devices), the midpoint of the transfer function is +2.5v. for the ?v and ?0v input range devices, the midpoint of the transfer function is zero. as shown in figure 2, there is a unity-gain buffer between ref ms and msv in the unipolar MAX1304/ max1305/max1306. this midscale buffer sets the mid- point of the unipolar transfer functions to either the inter- nal +2.5v reference or an externally applied voltage at ref ms . v msv follows v refms within ?mv. the midscale buffer is not active for the bipolar devices. for these devices, msv must be connected to agnd or externally driven. ref ms must be bypassed with a 0.01? capacitor to agnd. see the transfer functions section for more information about msv. table 3. reference bypass capacitors input voltage range location unipolar (?) bipolar (?) msv bypass capacitor to agnd 2.2 || 0.1 n/a ref ms bypass capacitor to agnd 0.01 0.01 ref bypass capacitor to agnd 0.01 0.01 ref+ bypass capacitor to agnd 0.1 0.1 ref+ to ref- capacitor 2.2 || 0.1 2.2 || 0.1 ref- bypass capacitor to agnd 0.1 0.1 com bypass capacitor to agnd 2.2 || 0.1 2.2 || 0.1 table 4. reference voltages parameter equation calculated value (v) v ref = 2.000v, av dd = 5.0v calculated value (v) v ref = 2.500v, av dd = 5.0v calculated value (v) v ref = 3.000v, av dd = 5.0v v com v com = 13 / 25 x av dd 2.600 2.600 2.600 v ref+ v ref+ = v com + v ref / 2 3.600 3.850 4.100 v ref- v ref- = v com - v ref / 2 1.600 1.350 1.100 v ref+ - v ref- v ref- - v ref+ = v ref 2.000 2.500 3.000 ( ) ( ) () n/a = not applicable. connect msv directly to agnd.
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 27 transfer functions unipolar 0 to +5v devices table 5 and figure 12 show the offset binary transfer function for the MAX1304/max1305/max1306 with a 0 to +5v input range. the full-scale input range (fsr) is two times the voltage at ref. the internal +2.5v refer- ence gives a +5v fsr, while an external +2v to +3v reference allows an fsr of +4v to +6v, respectively. calculate the lsb size using: which equals 1.22mv when using a 2.5v reference. the input range is centered about v msv , internally set to +2.5v. for a custom midscale voltage, drive ref ms with an external voltage source and msv will follow ref ms . noise present on msv or ref ms directly cou- ples into the adc result. use a precision, low-drift volt- age reference with adequate bypassing to prevent msv from degrading adc performance. for maximum fsr, do not violate the absolute maximum voltage ratings of the analog inputs when choosing msv. determine the input voltage as a function of v ref , v msv , and the output code in decimal using: v ch_ = lsb x code 10 + v msv - 2.500v 1 2 2 12 lsb xv ref = table 5. 0 to 5v unipolar code table binary digital output code decimal equivalent digital output code (code 10 ) input voltage (v) v ref = +2.5v v refms = +2.5v 1111 1111 1111 = 0xfff 4095 +4.9994 ?0.5 lsb 1111 1111 1110 = 0xffe 4094 +4.9982 ?0.5 lsb 1000 0000 0001 = 0x801 2049 +2.5018 ?0.5 lsb 1000 0000 0000 = 0x800 2048 +2.5006 ?0.5 lsb 0111 1111 1111 = 0x7ff 2047 +2.4994 ?0.5 lsb 0000 0000 0001 = 0x001 1 +0.0018 ?0.5 lsb 0000 0000 0000 = 0x000 0 +0.0006 ?0.5 lsb () 2 x v ref 2 x v ref 2 12 1 lsb = binary output code 02 1 3 4095 4093 0x0000 0x0001 0x0002 0x0003 0xfff 0xffe 0xffd 0xffc 0x7ff 0x800 0x801 2046 2048 2050 (msv) input voltage (lsbs) figure 12. 0 to +5v unipolar transfer function
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 28 ______________________________________________________________________________________ bipolar ?v devices table 6 and figure 13 show the two? complement trans- fer function for the ?v input range max1308/max1309/ max1310. the fsr is four times the voltage at ref. the internal +2.5v reference gives a +10v fsr, while an external +2v to +3v reference allows an fsr of +8v to +12v respectively. calculate the lsb size using: which equals 2.44mv when using a 2.5v reference. the input range is centered about v msv . normally, msv = agnd, and the input is symmetrical about zero. for a custom midscale voltage, drive msv with an external voltage source. noise present on msv directly couples into the adc result. use a precision, low- drift voltage reference with adequate bypassing to prevent msv from degrading adc performance. for maximum fsr, do not violate the absolute maximum voltage rat- ings of the analog inputs when choosing msv. determine the input voltage as a function of v ref , v msv , and the output code in decimal using: v ch_ = lsb x code 10 + v msv 1 4 2 12 lsb xv ref = table 6. 5v bipolar code table two? complement digital output code decimal equivalent digital output code (code 10 ) input voltage (v) v ref = +2.5v v msv = 0 0111 1111 1111 = 0x7ff +2047 +4.9988 ?0.5 lsb 0111 1111 1110 = 0x7fe +2046 +4.9963 ?0.5 lsb 0000 0000 0001 = 0x001 +1 +0.0037 ?0.5 lsb 0000 0000 0000 = 0x000 0 +0.0012 ?0.5 lsb 1111 1111 1111 = 0xfff -1 -0.0012 ?0.5 lsb 1000 0000 0001 = 0x801 -2047 -4.9963 ?0.5 lsb 1000 0000 0000 = 0x800 -2048 -4.9988 ?0.5 lsb ( ) 4 x v ref 4 x v ref 2 12 1 lsb = two's complement binary output code -2048 -2046 +2047 +2045 0x800 0x801 0x802 0x803 0x7ff 0x7fe 0x7fd 0x7fc 0xfff 0x000 0x001 -1 0 +1 (msv) input voltage (v ch_ - v msv in lsbs) figure 13. ?v bipolar transfer function
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 29 bipolar ?0v devices table 7 and figure 14 show the two? complement trans- fer function for the ?0v input range max1312/ max1313/max1314. the fsr is eight times the voltage at ref. the internal +2.5v reference gives a +20v fsr, while an external +2v to +3v reference allows an fsr of +16v to +24v, respectively. calculate the lsb size using: which equals 4.88mv with a +2.5v internal reference. the input range is centered about v msv . normally, msv = agnd, and the input is symmetrical about zero. for a custom midscale voltage, drive msv with an external voltage source. noise present on msv directly couples into the adc result. use a precision, low- drift voltage reference with adequate bypassing to prevent msv from degrading adc performance. for maximum fsr, do not violate the absolute maximum voltage rat- ings of the analog inputs when choosing msv. determine the input voltage as a function of v ref , v msv , and the output code in decimal using: v ch_ = lsb x code 10 + v msv 1 8 2 12 lsb xv ref = table 7. 10v bipolar code table two? complement digital output code decimal equivalent digital output code (code 10 ) input voltage (v) v ref = +2.5v v msv = 0 0111 1111 1111 = 0x7ff +2047 +9.9976 ?0.5 lsb 0111 1111 1110 = 0x7fe +2046 +9.9927 ?0.5 lsb 0000 0000 0001 = 0x001 +1 +0.0073 ?0.5 lsb 0000 0000 0000 = 0x000 0 0.0024 ?0.5 lsb 1111 1111 1111 = 0xfff -1 -0.0024 ?0.5 lsb 1000 0000 0001 = 0x801 -2047 -9.9927 ?0.5 lsb 1000 0000 0000 = 0x800 -2048 -9.9976 ?0.5 lsb () 8 x v ref 8 x v ref 2 12 1 lsb = two's complement binary output code -2048 -2046 +2047 +2045 0x800 0x801 0x802 0x803 0x7ff 0x7fe 0x7fd 0x7fc 0xfff 0x000 0x001 -1 0 +1 (msv) input voltage (v ch_ - v msv in lsbs) figure 14. ?0v bipolar transfer function
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 30 ______________________________________________________________________________________ 3-phase motor controller the MAX1304?ax1306/max1308?ax1310/max1312 max1314 are ideally suited for motor-control systems (figure 15). the devices?simultaneously sampled inputs eliminate the need for complicated dsp algo- rithms that realign sequentially sampled data into a simultaneous sample set. additionally, the variety of input voltage ranges allows for flexibility when choosing current sensors and position encoders. 12-bit adc dsp current sensor i phase1 phase 1 phase 2 phase 3 3-phase electric motor position encoder i phase3 i phase2 igbt current drivers t/h max1308 figure 15. 3-phase motor control
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 31 3-phase power-monitoring system the 8-channel devices are well suited for use in 3-phase power monitoring (figure 16). the simultane- ously sampled eight channels eliminate the need for complicated dsp algorithms that realign sequentially sampled data into a simultaneous sample set. 12-bit adc microcontroller load i p1 i p2 i p3 v p2 phase 1 neutral phase 2 phase 3 v p1 v neutral v p3 buffers and input protection i pn t/h current transformer current transformer current transformer current transformer power grid max1312 load load figure 16. 3-phase power monitoring
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 32 ______________________________________________________________________________________ layout, grounding, and bypassing for best performance use pc boards. board layout must ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines paral- lel to one another (especially clock lines), and do not run digital lines underneath the adc package. figure 17 shows the recommended system ground con- nections. establish an analog ground point at agnd and a digital ground point at dgnd. connect all analog grounds to the analog ground point. connect all digital grounds to the digital ground point. for lowest noise operation, make the power-supply ground returns as low impedance and as short as possible. connect the analog ground point to the digital ground point at one location. high-frequency noise in the power supplies degrades the adc? performance. bypass the analog power plane to the analog ground plane with a 2.2? capaci- tor within one inch of the device. bypass each av dd to agnd pair of pins with a 0.1? capacitor as close to the device as possible. av dd to agnd pairs are pin 1 to pin 2, pin 14 to pin 15, and pin 16 to pin 17. likewise, bypass the digital power plane to the digital ground plane with a 2.2? capacitor within one inch of the device. bypass each dv dd to dgnd pair of pins with a 0.1? capacitor as close to the device as possi- ble. dv dd to dgnd pairs are pin 24 to pin 25, and pin 38 to pin 39. if a supply is very noisy use a ferrite bead as a lowpass filter as shown in figure 17. definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst- case value is reported in the electrical characteristics table. a dnl error specification of less than ? lsb guarantees no missing codes and a monotonic transfer function. offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. typically the point at which offset error is specified is either at or near the zero- scale point of the transfer function or at or near the mid- scale point of the transfer function. for the unipolar devices (MAX1304/max1305/ max1306), the ideal zero-scale transition from 0x000 to 0x001 occurs at 1 lsb above agnd (figure 12, table 5). unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point. for the bipolar devices (max1308/max1309/max1310/ max1312/max1313/max1314), the ideal midscale tran- sition from 0xfff to 0x000 occurs at msv (figures 14 and 13, tables 7 and 6). the bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. analog supply av dd agnd dv dd data dgnd digital circuitry optional ferrite bead +5v return digital ground point digital supply return +3v to +5v dgnd dv dd MAX1304?ax1306 max1308?ax1310 max1312?ax1314 analog ground point figure 17. power-supply grounding and bypassing
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 33 gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. for the MAX1304 max1306/max1308?ax1310/max1312?ax1314, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. for the unipolar devices (MAX1304/max1305/ max1306), the full-scale transition point is from 0xffe to 0xfff and the zero-scale transition point is from 0x000 to 0x001. for the bipolar devices (max1308/max1309/max1310/ max1312/max1313/max1314), the full-scale transition point is from 0x7fe to 0x7ff and the zero-scale transi- tion point is from 0x800 to 0x801. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db n + 1.76 db in reality, there are other noise sources such as thermal noise, reference noise, and clock jitter. for these devices, snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist fre- quency excluding the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus distor- tion includes all spectral components to the nyquist fre- quency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed as: total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmon- ics to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 6 are the amplitudes of the 2nd- through 6th- order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the fundamen- tal (maximum signal component) to the rms value of the next largest spurious component, excluding dc offset. sfdr is specified in decibels relative to the carrier (dbc). channel-to-channel isolation channel-to-channel isolation indicates how well each analog input is isolated from the others. the channel-to- channel isolation for these devices is measured by applying dc to channel 1 through channel 7 while an ac 500khz, -0.4dbfs sine wave is applied to channel 0. an fft is taken for channel 0 and channel 1 and the difference (in db) of the 500khz magnitudes is reported as the channel-to-channel isolation. aperature delay aperture delay (t ad ) is the time delay from the convst rising edge to the instant when an actual sample is taken. thd x vvvvv v = ++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 1 log enob sinad = ? 176 602 . . sinad db x signal noise distortion rms rms () log () = + ? ? ? ? ? ? 20
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges 34 ______________________________________________________________________________________ aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. jitter is a concern when considering an adc? dynamic performance, e.g., snr. to reconstruct an analog input from the adc digital outputs, it is critical to know the time at which each sample was taken. typical applica- tions use an accurate sampling clock signal that has low jitter from sampling edge to sampling edge. for a system with a perfect sampling clock signal, with no clock jitter, the snr performance of an adc is limited by the adc? internal aperture jitter as follows: where f in represents the analog input frequency and t aj is the time of the aperture jitter. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc so that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. full-power bandwidth a large, -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. dc power-supply rejection (psrr) dc psrr is defined as the change in the positive full- scale transfer function point caused by a ?% variation in the analog power-supply voltage (av dd ). chip information transistor count: 50,000 process: 0.6? bicmos snr x xxfxt in aj = ? ? ? ? ? ? 20 1 2 log
d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv dd av dd agnd agnd ch0 ch1 msv ch2 ch3 ch4 ch5 ch6 ch7 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 8-channel tqfp MAX1304 max1308 max1312 intclk/extclk agnd av dd agnd av dd ref ms ref ref+ com ref- agnd dgnd 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 chshdn shdn clk convst cs wr rd eolc eoc dgnd dv dd d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv dd av dd agnd agnd ch0 ch1 msv ch2 ch3 i.c. i.c. i.c. i.c. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 4-channel tqfp max1305 max1309 max1313 intclk/extclk agnd av dd agnd av dd ref ms ref ref+ com ref- agnd dgnd 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 chshdn shdn clk convst cs wr rd eolc eoc dgnd dv dd d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv dd av dd agnd agnd ch0 ch1 msv i.c. i.c. i.c. i.c. i.c. i.c. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 2-channel tqfp max1306 max1310 max1314 intclk/extclk agnd av dd agnd av dd ref ms ref ref+ com ref- agnd dgnd 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 chshdn shdn clk convst cs wr rd eolc eoc dgnd dv dd d11 top view MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges ______________________________________________________________________________________ 35 pin configurations
MAX1304?ax1306/max1308?ax1310/max1312?ax1314 8-/4-/2-channel, 12-bit, simultaneous-sampling adcs with ?0v, ?v, and 0 to +5v analog input ranges maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32l/48l,tqfp.eps

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